Secure Integration Framework for Heterogeneous Chiplet-Based Systems

During the research we will study different hardware threats and their effects on chiplets based systems, and we will attempt to propose a way of integration that can mitigate or prevent those threats, the proposed security model will attempt to detect threats in a real-time fashion and try to ensure that the passing of data between different chiplets doesn’t alter it or expose it, ensuring data integrity and confidentiality, we will be using simulation tools such as Verilog and System C for the architectural modeling, and we will follow UVM (universal verification methodology) for our functional verification and code coverage of the proposed architecture, we will also consider proving the effectiveness of the approach via formal verification. The evaluation of the proposed architecture will be measured by testing the endurance of the system against very famous attacks and exposure patterns, and how they affect the system performance and power consumption theoretically. The outcome of this research will be a comprehensive over-view of security threats against heterogeneous chiplets systems, as well as a proposal for a secure architecture that will allow for the perseverance of data and its security